The present invention relates, in general, to an electronic package for mounting of integrated circuits, and in particular, to an organic multi-layered interconnect structure for use in such a package.
Organic substrates for example printed circuit boards and chip carriers have been and continue to be developed for many applications. These are expected to displace ceramic substrates, in particular in many chip carrier applications, because of reduced cost and enhanced electrical performance. The use of a multi-layered interconnect structure such as an organic chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package introduces many challenges, one of which is the reliability of the connection joints between the semiconductor chip and the organic chip carrier and another of which is the reliability of the connection joints between the organic chip carrier and the printed circuit board.
As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects are the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier and between the organic chip carrier and a printed circuit board. If the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier can exhibit high stress during operation (thermal cycling). Similarly, the industry standard ball grid array (BGA) interconnections between the organic chip carrier and printed circuit board can also exhibit high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (chip cracking). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the electronic package. Typically a semiconductor chip has a CTE of 2-3parts per million per degree Celsius (ppm/xc2x0 C.) while a standard printed circuit board has a much greater CTE of 17-20 ppm/xc2x0 C.
It is therefore desirable to reliably interconnect a semiconductor chip to a printed circuit substrate or board in a fashion that significantly improves electrical performance . An electronic package that includes a multi-layered interconnect structure, an organic chip carrier that is relatively compliant and made by selecting the materials and thickness of the materials to yield a chip carrier CTE of only about 10-12 ppm/xc2x0 C., can substantially prevent failure of the interconnections between the semiconductor chip and the organic chip carrier and between the organic chip carrier and the printed circuit board. Furthermore, it can enable design of the electronic package to significantly improve electrical performance. It is believed that such a structure and method for making same would constitute a significant art advancement.
Accordingly, it is an object of this invention to enhance the art of electronic packaging by providing an electronic package with significantly improved electrical performance.
Another object of this invention is to provide a multi-layered interconnect structure for use in an electronic package, the multi-layered interconnect structure including a thermally conductive layer comprised of a material having a thickness and coefficient of thermal expansion to substantially prevent failure of solder connections between a semiconductor chip and a circuitized substrate.
Yet another object of this invention is to provide an electronic package having a semiconductor chip with a plurality of contact members connected by solder connections to a multi-layered interconnect structure.
Still yet another object of this invention is to provide a method of making such an electronic package having a multi-layered interconnect structure that is relatively compliant and includes a CTE so as to substantially prevent failure of solder connections between the semiconductor chip and the multi-layered interconnect structure.
Another object is to provide such a method and structure that are both adaptable to mass production, thus assuring lower costs.
According to one aspect of the invention, there is provided a multi-layered interconnect structure adapted for electrically interconnecting a semiconductor chip and a circuitized substrate using solder connections, the multi-layered interconnect structure comprising a thermally conductive layer including first and second opposing surfaces and first and second dielectric layers positioned on the first and second opposing surfaces, respectively. The multi-layered interconnect structure includes first and second pluralities of electrically conductive members positioned on the first and second dielectric layers, respectively, each of the first and second pluralities of the electrically conductive members being adapted for having solder connections thereon, for being electrically connected to a semiconductor chip and a circuitized substrate, respectively. The thermally conductive layer is comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between the first plurality of electrically conductive members and the semiconductor chip and between the second plurality of electrically conductive members and the circuitized substrate.
According to another aspect of the invention there is provided a method of making a multi-layered interconnect structure adapted for electrically interconnecting a semiconductor chip and a circuitized substrate using solder connections, the method comprising the steps of providing a thermally conductive layer including first and second opposing surfaces and positioning first and second dielectric layers on the first and second opposing surfaces of the thermally conductive layer, respectively. The method further includes the step of positioning first and second pluralities of electrically conductive members on the first and second dielectric layers, respectively, each of the first and second pluralities of the electrically conductive members being adapted for having solder connections thereon for being electrically connected to a semiconductor chip and a circuitized substrate, respectively. The thermally conductive layer is comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between the first plurality of electrically conductive members and the semiconductor chip and between the second plurality of electrically conductive members and the circuitized substrate.
According to yet another aspect of the invention, there is provided an electronic package comprising a semiconductor chip having a first surface, the first surface including a plurality of contact members, and a multi-layered interconnect structure adapted for electrically interconnecting the semiconductor chip to a circuitized substrate. The multi-layered interconnect structure includes a thermally conductive layer having first and second opposing surfaces, first and second dielectric layers positioned on the first and second opposing surfaces, respectively, and first and second pluralities of electrically conductive members positioned on the first and second dielectric layers, respectively. The first plurality of electrically conductive members includes a plurality of solder connections electrically connected thereto, respective ones of the solder connections being electrically connected to respective ones of the plurality of contact members on the semiconductor chip. The thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between the first plurality of electrically conductive members and the semiconductor chip.
According to still yet another aspect of the invention, there is provided a method of making an electronic package comprising the steps of providing a semiconductor chip having a first surface, the first surface including a plurality of contact members thereon and providing a multi-layered interconnect structure adapted for electrically interconnecting the semiconductor chip to a circuitized substrate, the multi-layered interconnect structure including a thermally conductive layer, having first and second opposing surfaces, first and second dielectric layers positioned on the first and second opposing surfaces, respectively, and first and second pluralities of electrically conductive members positioned on the first and second dielectric layers, respectively. The method further includes the step of providing a first plurality of solder connections on the first plurality of electrically conductive members and connecting respective ones of the first plurality of solder connections to respective ones of the plurality of contact members on the semiconductor chip. The thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between the first plurality of electrically conductive members and the semiconductor chip.